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CSD87330Q3D www.ti.com slps284b C august 2011 C revised september 2011 synchronous buck nexfet ? power block 1 features description the CSD87330Q3D nexfet ? power block is an 2 ? half-bridge power block optimized design for synchronous buck applications ? up to 27v v in offering high current, high efficiency, and high ? 90% system efficiency at 15a frequency capability in a small 3.3-mm 3.3-mm outline. optimized for 5v gate drive applications, this ? up to 20a operation product offers a flexible solution capable of offering a ? high frequency operation (up to 1.5mhz) high density power supply when paired with any 5v ? high density C son 3.3-mm 3.3-mm gate drive from an external controller/driver. footprint text added for spacing ? optimized for 5v gate drive top view ? low switching losses ? ultra low inductance package ? rohs compliant ? halogen free ? pb-free terminal plating text added for spacing applications ordering information ? synchronous buck converters device package media qty ship C high frequency applications son 13-inch tape and CSD87330Q3D 3.3-mm 3.3-mm 2500 C high current, low duty cycle applications reel reel plastic package ? multiphase synchronous buck converters ? pol dc-dc converters ? imvp, vrm, and vrd applications text added for spacing text added for spacing text added for spacing typical power block efficiency typical circuit and power loss 1 please be aware that an important notice concerning availability, standard warranty, and use in critical applications of texas instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. 2 nexfet is a trademark of texas instruments. production data information is current as of publication date. copyright ? 2011, texas instruments incorporated products conform to specifications per the terms of the texas instruments standard warranty. production processing does not necessarily include testing of all parameters. p0116-01 1 2 3 v sw v sw v sw 4 b g 5 t gr 6 t g p gnd (pin 9) 7 v in 8 v in 0 5 10 15 20 40 50 60 70 80 90 100 0 1 2 3 4 5 6 output current (a) efficiency (%) power loss (w) v gs = 5v v in = 12v v out = 1.3v l out = 1.0h f sw = 500khz t a = 25oc
CSD87330Q3D slps284b C august 2011 C revised september 2011 www.ti.com these devices have limited built-in esd protection. the leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the mos gates. absolute maximum ratings t a = 25 c (unless otherwise noted) (1) value unit parameter conditions min max v in to p gnd 30 v v sw to p gnd 30 v voltage range v sw to p gnd (10ns) 32 v t g to t gr -8 10 v b g to p gnd -8 10 v pulsed current rating, i dm 60 a power dissipation, p d 6 w sync fet, i d = 56a, l = 0.1mh 157 avalanche energy e as mj control fet, i d = 36a, l = 0.1mh 65 operating junction and storage temperature range, t j , t stg C 55 150 c (1) stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. recommended operating conditions t a = 25 (unless otherwise noted) parameter conditions min max unit gate drive voltage, v gs 4.5 8 v input supply voltage, v in 27 v switching frequency, f sw c bst = 0.1 f (min) 1500 khz operating current 20 a operating temperature, t j 125 c power block performance (1) t a = 25 (unless otherwise noted) parameter conditions min typ max unit v in = 12v, v gs = 5v, v out = 1.3v, power loss, p loss (1) i out = 15a, f sw = 500khz, 2 w l out = 1 h, t j = 25 o c v in quiescent current, i qvin t g to t gr = 0v b g to p gnd = 0v 10 a (1) measurement made with six 10- f (tdk c3216x5r1c106kt or equivalent) ceramic capacitors placed across v in to p gnd pins and using a high current 5v driver ic. thermal information t a = 25 c (unless otherwise stated) thermal metric min typ max unit junction to ambient thermal resistance (min cu) (1) 135 r ja junction to ambient thermal resistance (max cu) (1) (2) 73 c/w junction to case thermal resistance (top of package) (1) 29 r jc junction to case thermal resistance (p gnd pin) (1) 2.5 (1) r jc is determined with the device mounted on a 1-inch 2 (6.45-cm 2 ), 2 oz. (0.071-mm thick) cu pad on a 1.5-inch 1.5-inch (3.81-cm 3.81-cm), 0.06-inch (1.52-mm) thick fr4 board. r jc is specified by design while r ja is determined by the user s board design. (2) device mounted on fr4 material with 1-inch 2 (6.45-cm 2 ) cu. 2 submit documentation feedback copyright ? 2011, texas instruments incorporated
CSD87330Q3D www.ti.com slps284b C august 2011 C revised september 2011 electrical characteristics t a = 25 c (unless otherwise stated) q1 control fet q2 sync fet parameter test conditions min typ max min typ max unit static characteristics bv dss drain to source voltage v gs = 0v, i ds = 250 a 30 30 v drain to source leakage i dss v gs = 0v, v ds = 20v 1 1 a current gate to source leakage i gss v ds = 0v, v gs = +10 / C 8 100 100 na current gate to source threshold v gs(th) v ds = v gs , i ds = 250 a 1 2.1 0.75 1.15 v voltage v in = 12v, v gs = 5v, v out = 1.3v, i out = 15a, z ds(on) effective ac on-impedance 9.45 3.6 m ? f sw = 500khz, l out = 1 h g fs transconductance v ds = 15v, i ds = 15a 51 76 s dynamic characteristics c iss input capacitance 750 900 1360 1632 pf c oss output capacitance v gs = 0v, v ds = 15v, 310 370 580 700 pf f = 1mhz reverse transfer c rss 13 16 35 44 pf capacitance r g series gate resistance 1.5 3 0.8 1.6 q g gate charge total (4.5v) 4.8 5.8 9.6 11.5 nc q gd gate charge - gate to drain 0.9 1.8 nc v ds = 15v, gate charge - gate to i ds = 15a q gs 1.5 2 nc source q g(th) gate charge at vth 0.9 1.1 nc q oss output charge v ds = 14v, v gs = 0v 6 11 nc t d(on) turn on delay time 4.5 4.5 ns t r rise time 6.8 7.5 ns v ds = 15v, v gs = 4.5v, i ds = 15a, r g = 2 ? t d(off) turn off delay time 9.4 9.1 ns t f fall time 1.7 1.6 ns diode characteristics v sd diode forward voltage i ds = 15a, v gs = 0v 0.85 1 0.85 1 v q rr reverse recovery charge 10 15 nc v ds = 14v, i f = 15a, di/dt = 300a/ s t rr reverse recovery time 14 18 ns max r ja = 73 c/w max r ja = 135 c/w when mounted on when mounted on 1 inch 2 (6.45 cm 2 ) of minimum pad area of 2-oz. (0.071-mm thick) 2-oz. (0.071-mm thick) cu. cu. copyright ? 2011, texas instruments incorporated submit documentation feedback 3 hd hg lg ld m0205-01 86330q3d 3 3x3 3 min rev0 . . ls hs hd hg lg ld m0206-01 86330q3d 3 3x3 3 min rev0 . . ls hs
CSD87330Q3D slps284b C august 2011 C revised september 2011 www.ti.com typical power block device characteristics test conditions: v in = 12v, v dd = 5v, f sw = 500khz, v out = 1.3v, l out = 1 h, i out = 20a, t j = 125 c, unless stated otherwise. figure 1. power loss vs output current figure 2. power loss vs temperature figure 3. safe operating area C pcb vertical mount (1) figure 4. safe operating area C pcb horizontal mount (1) figure 5. typical safe operating area (1) (1) the typical power block system characteristic curves are based on measurements made on a pcb design with dimensions of 4.0 (w) 3.5 (l) 0.062 (h) and 6 copper layers of 1 oz. copper thickness. see application section for detailed explanation. 4 submit documentation feedback copyright ? 2011, texas instruments incorporated 0 5 10 15 20 25 0 20 40 60 80 100 120 140 board temperature (oc) output current (a) 0 1 2 3 4 5 0 2 4 6 8 10 12 14 16 18 20 output current (a) power loss (w) 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 ?50 ?25 0 25 50 75 100 125 150 junction temperature (oc) power loss, normalized 0 5 10 15 20 25 0 10 20 30 40 50 60 70 80 90 ambient temperature (oc) output current (a) 400lfm200lfm 100lfm nat conv 0 5 10 15 20 25 0 10 20 30 40 50 60 70 80 90 ambient temperature (oc) output current (a) 400lfm200lfm 100lfm nat conv
CSD87330Q3D www.ti.com slps284b C august 2011 C revised september 2011 typical power block device characteristics (continued) test conditions: v in = 12v, v dd = 5v, f sw = 500khz, v out = 1.3v, l out = 1 h, i out = 20a, t j = 125 c, unless stated otherwise. text added for spacing text added for spacing figure 6. normalized power loss vs switching frequency figure 7. normalized power loss vs input voltage text added for spacing text added for spacing figure 8. normalized power loss vs. output voltage figure 9. normalized power loss vs. output inductance copyright ? 2011, texas instruments incorporated submit documentation feedback 5 200 350 500 650 800 950 1100 1250 1400 1550 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 ?10.3 ?7.7 ?5.2 ?2.6 0.0 2.6 5.2 7.7 10.3 12.9 15.5 switching frequency (khz) power loss, normalized soa temperature adj (oc) 3 5 7 9 11 13 15 17 19 21 23 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 ?10.3 ?7.7 ?5.1 ?2.6 0.0 2.6 5.1 7.7 10.3 12.9 15.4 input voltage (v) power loss, normalized soa temperature adj (oc) 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 5.5 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 ?10.3 ?7.7 ?5.1 ?2.6 0 2.6 5.1 7.7 10.3 12.8 15.4 output voltage (v) power loss, normalized soa temperature adj (oc) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 0.6 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 1.5 1.6 ?10.1 ?7.5 ?5 ?2.5 0 2.5 5.1 7.6 10.1 12.6 15.1 output inductance (h) power loss, normalized soa temperature adj (oc)
CSD87330Q3D slps284b C august 2011 C revised september 2011 www.ti.com typical power block mosfet characteristics t a = 25 c, unless stated otherwise. text added for spacing text added for spacing figure 10. control mosfet saturation figure 11. sync mosfet saturation text added for spacing text added for spacing figure 12. control mosfet transfer figure 13. sync mosfet transfer text added for spacing text added for spacing figure 14. control mosfet gate charge figure 15. sync mosfet gate charge 6 submit documentation feedback copyright ? 2011, texas instruments incorporated 0 10 20 30 40 50 60 70 80 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 v ds - drain-to-source voltage - v i ds - drain-to-source current - a v gs = 8.0v v gs = 4.5v v gs = 4.0v 0 10 20 30 40 50 60 70 80 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 v ds - drain-to-source voltage - v i ds - drain-to-source current - a v gs = 8.0v v gs = 4.5v v gs = 4.0v 0.001 0.01 0.1 1 10 100 0.5 1 1.5 2 2.5 3 3.5 v gs - gate-to-source voltage - v i ds - drain-to-source current - a t c = 125c t c = 25c t c = ?55c v ds = 5v 0.001 0.01 0.1 1 10 100 0 0.5 1 1.5 2 2.5 3 v gs - gate-to-source voltage - v i ds - drain-to-source current - a t c = 125c t c = 25c t c = ?55c v ds = 5v 0 1 2 3 4 5 6 7 8 0 1 2 3 4 5 6 7 8 9 10 q g - gate charge - nc (nc) v gs - gate-to-source voltage (v) i d = 15a v dd = 15v 0 1 2 3 4 5 6 7 8 0 2 4 6 8 10 12 14 16 18 q g - gate charge - nc (nc) v gs - gate-to-source voltage (v) i d = 15a v dd = 15v
CSD87330Q3D www.ti.com slps284b C august 2011 C revised september 2011 typical power block mosfet characteristics (continued) t a = 25 c, unless stated otherwise. text added for spacing text added for spacing figure 16. control mosfet capacitance figure 17. sync mosfet capacitance text added for spacing text added for spacing figure 18. control mosfet v gs(th) figure 19. sync mosfet v gs(th) text added for spacing text added for spacing figure 20. control mosfet r ds(on) vs v gs figure 21. sync mosfet r ds(on) vs v gs copyright ? 2011, texas instruments incorporated submit documentation feedback 7 0.001 0.01 0.1 1 10 0 5 10 15 20 25 30 v ds - drain-to-source voltage - v c ? capacitance ? nf c iss = c gd + c gs c oss = c ds + c gd c rss = c gd f = 1mhzv gs = 0v 0.001 0.01 0.1 1 10 0 5 10 15 20 25 30 v ds - drain-to-source voltage - v c ? capacitance ? nf c iss = c gd + c gs c oss = c ds + c gd c rss = c gd f = 1mhzv gs = 0v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 ?75 ?25 25 75 125 175 t c - case temperature - oc v gs ( th ) - threshold voltage - v i d = 250a 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 ?75 ?25 25 75 125 175 t c - case temperature - oc v gs ( th ) - threshold voltage - v i d = 250a 0 5 10 15 20 25 30 0 1 2 3 4 5 6 7 8 9 10 v gs - gate-to- source voltage - v r ds ( on ) - on-state resistance - m w t c = 25c t c = 125oc i d = 15a 0 2 4 6 8 10 12 14 16 18 20 0 1 2 3 4 5 6 7 8 9 10 v gs - gate-to- source voltage - v r ds ( on ) - on-state resistance - m w t c = 25c t c = 125oc i d = 15a
CSD87330Q3D slps284b C august 2011 C revised september 2011 www.ti.com typical power block mosfet characteristics (continued) t a = 25 c, unless stated otherwise. text added for spacing text added for spacing figure 22. control mosfet normalized r ds(on) figure 23. sync mosfet normalized r ds(on) text added for spacing text added for spacing figure 24. control mosfet body diode figure 25. sync mosfet body diode text added for spacing text added for spacing figure 26. control mosfet unclamped inductive figure 27. sync mosfet unclamped inductive switching switching 8 submit documentation feedback copyright ? 2011, texas instruments incorporated 1 10 100 1000 0.01 0.1 1 10 t ( av ) - time in avalanche - ms i ( av ) - peak avalanche current - a t c = 25c t c = 125c 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 ?75 ?25 25 75 125 175 t c - case temperature - oc normalized on-state resistance i d = 15a v gs = 4.5v 0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 ?75 ?25 25 75 125 175 t c - case temperature - oc normalized on-state resistance i d = 15a v gs = 4.5v 0.0001 0.001 0.01 0.1 1 10 100 0 0.2 0.4 0.6 0.8 1 1.2 v sd ? source-to-drain voltage - v i sd ? source-to-drain current - a t c = 25c t c = 125c 0.0001 0.001 0.01 0.1 1 10 100 0 0.2 0.4 0.6 0.8 1 1.2 v sd ? source-to-drain voltage - v i sd ? source-to-drain current - a t c = 25c t c = 125c 1 10 100 1000 0.01 0.1 1 10 t ( av ) - time in avalanche - ms i ( av ) - peak avalanche current - a t c = 25c t c = 125c
CSD87330Q3D www.ti.com slps284b C august 2011 C revised september 2011 application information equivalent system performance many of today s high performance computing systems require low power consumption in an effort to reduce system operating temperatures and improve overall system efficiency. this has created a major emphasis on improving the conversion efficiency of today s synchronous buck topology. in particular, there has been an emphasis in improving the performance of the critical power semiconductor in the power stage of this application (see figure 28 ). as such, optimization of the power semiconductors in these applications, needs to go beyond simply reducing r ds(on) . figure 28. the CSD87330Q3D is part of ti s power block product family which is a highly optimized product for use in a synchronous buck topology requiring high current, high efficiency, and high frequency. it incorporates ti s latest generation silicon which has been optimized for switching performance, as well as minimizing losses associated with q gd , q gs , and q rr . furthermore, ti s patented packaging technology has minimized losses by nearly eliminating parasitic elements between the control fet and sync fet connections (see figure 29 ). a key challenge solved by ti s patented packaging technology is the system level impact of common source inductance (csi). csi greatly impedes the switching characteristics of any mosfet which in turn increases switching losses and reduces system efficiency. as a result, the effects of csi need to be considered during the mosfet selection process. in addition, standard mosfet switching loss equations used to predict system efficiency need to be modified in order to account for the effects of csi. further details behind the effects of csi and modification of switching loss equations are outlined in ti s application note slpa009 . figure 29. copyright ? 2011, texas instruments incorporated submit documentation feedback 9
CSD87330Q3D slps284b C august 2011 C revised september 2011 www.ti.com the combination of ti s latest generation silicon and optimized packaging technology has created a benchmarking solution that outperforms industry standard mosfet chipsets of similar r ds(on) and mosfet chipsets with lower r ds(on) . figure 30 and figure 31 compare the efficiency and power loss performance of the CSD87330Q3D versus industry standard mosfet chipsets commonly used in this type of application. this comparison purely focuses on the efficiency and generated loss of the power semiconductors only. the performance of CSD87330Q3D clearly highlights the importance of considering the effective ac on-impedance (z ds(on) ) during the mosfet selection process of any new design. simply normalizing to traditional mosfet r ds(on) specifications is not an indicator of the actual in-circuit performance when using ti s power block technology. figure 30. figure 31. the chart below compares the traditional dc measured r ds(on) of CSD87330Q3D versus its z ds(on) . this comparison takes into account the improved efficiency associated with ti s patented packaging technology. as such, when comparing ti s power block products to individually packaged discrete mosfets or dual mosfets in a standard package, the in-circuit switching performance of the solution must be considered. in this example, individually packaged discrete mosfets or dual mosfets in a standard package would need to have dc measured r ds(on) values that are equivalent to CSD87330Q3D s z ds(on) value in order to have the same efficiency performance at full load. mid to light-load efficiency will still be lower with individually packaged discrete mosfets or dual mosfets in a standard package. comparison of r ds(on) vs. z ds(on) hs ls parameter typ max typ max effective ac on-impedance z ds(on) (v gs = 5v) 9.4 - 3.6 - dc measured r ds(on) (v gs = 4.5v) 9.4 11.3 4.7 5.7 10 submit documentation feedback copyright ? 2011, texas instruments incorporated 80 82 84 86 88 90 92 94 96 0 5 10 15 20 25 output current (a) efficiency (%) powerblock hs/ls r ds ( on ) = 9.4m w /4.7m w discrete hs/ls r ds ( on ) = 9.4m w /4.7m w discrete hs/ls r ds ( on ) = 9.4m w /3.6m w v gs = 5v v in = 12v v out = 1.3v l out = 1h f sw = 500khz t a = 25oc 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 0 5 10 15 20 25 output current (a) power loss (w) powerblock hs/ls r ds ( on ) = 9.4m w /4.7m w discrete hs/ls r ds ( on ) = 9.4m w /4.7m w discrete hs/ls r ds ( on ) = 9.4m w /3.6m w v gs = 5v v in = 12v v out = 1.3v l out = 1h f sw = 500khz t a = 25oc
CSD87330Q3D www.ti.com slps284b C august 2011 C revised september 2011 the CSD87330Q3D nexfet ? power block is an optimized design for synchronous buck applications using 5v gate drive. the control fet and sync fet silicon are parametrically tuned to yield the lowest power loss and highest system efficiency. as a result, a new rating method is needed which is tailored towards a more systems centric environment. system level performance curves such as power loss, safe operating area, and normalized graphs allow engineers to predict the product performance in the actual application. power loss curves mosfet centric parameters such as r ds(on) and q gd are needed to estimate the loss generated by the devices. in an effort to simplify the design process for engineers, texas instruments has provided measured power loss performance curves. figure 1 plots the power loss of the CSD87330Q3D as a function of load current. this curve is measured by configuring and running the CSD87330Q3D as it would be in the final application (see figure 32 ).the measured power loss is the CSD87330Q3D loss and consists of both input conversion loss and gate drive loss. equation 1 is used to generate the power loss curve. (v in i in ) + (v dd i dd ) C (v sw_avg i out ) = power loss (1) the power loss curve in figure 1 is measured at the maximum recommended junction temperatures of 125 c under isothermal test conditions. safe operating curves (soa) the soa curves in the CSD87330Q3D data sheet provides guidance on the temperature boundaries within an operating system by incorporating the thermal resistance and system power loss. figure 3 to figure 5 outline the temperature and airflow conditions required for a given load current. the area under the curve dictates the safe operating area. all the curves are based on measurements made on a pcb design with dimensions of 4 (w) 3.5 (l) 0.062 (t) and 6 copper layers of 1 oz. copper thickness. normalized curves the normalized curves in the CSD87330Q3D data sheet provides guidance on the power loss and soa adjustments based on their application specific needs. these curves show how the power loss and soa boundaries will adjust for a given set of systems conditions. the primary y-axis is the normalized change in power loss and the secondary y-axis is the change is system temperature required in order to comply with the soa curve. the change in power loss is a multiplier for the power loss curve and the change in temperature is subtracted from the soa curve. figure 32. typical application copyright ? 2011, texas instruments incorporated submit documentation feedback 11
CSD87330Q3D slps284b C august 2011 C revised september 2011 www.ti.com calculating power loss and soa the user can estimate product loss and soa boundaries by arithmetic means (see design example). though the power loss and soa curves in this data sheet are taken for a specific set of test conditions, the following procedure will outline the steps the user should take to predict product performance for any set of system conditions. design example operating conditions: ? output current = 15a ? input voltage = 12v ? output voltage = 1.2v ? switching frequency = 1000khz ? inductor = 0.4 h calculating power loss ? power loss at 15a = 2.2w ( figure 1 ) ? normalized power loss for input voltage 1.0 ( figure 7 ) ? normalized power loss for output voltage 0.98 ( figure 8 ) ? normalized power loss for switching frequency 1.17 ( figure 6 ) ? normalized power loss for output inductor 1.06 ( figure 9 ) ? final calculated power loss = 2.2w 1.0 0.98 1.17 1.06 2.67w calculating soa adjustments ? soa adjustment for input voltage 0 o c ( figure 7 ) ? soa adjustment for output voltage C 0.29 o c ( figure 8 ) ? soa adjustment for switching frequency 4.1 o c ( figure 6 ) ? soa adjustment for output inductor 1.5 o c ( figure 9 ) ? final calculated soa adjustment = 0 + ( C 0.29) + 4.1 + 1.5 5.3 o c in the design example above, the estimated power loss of the CSD87330Q3D would increase to 2.67w. in addition, the maximum allowable board and/or ambient temperature would have to decrease by 5.3 o c. figure 33 graphically shows how the soa curve would be adjusted accordingly. 1. start by drawing a horizontal line from the application current to the soa curve. 2. draw a vertical line from the soa curve intercept down to the board/ambient temperature. 3. adjust the soa board/ambient temperature by subtracting the temperature adjustment value. in the design example, the soa temperature adjustment yields a reduction in allowable board/ambient temperature of 5.3 o c. in the event the adjustment value is a negative number, subtracting the negative number would yield an increase in allowable board/ambient temperature. figure 33. power block soa 12 submit documentation feedback copyright ? 2011, texas instruments incorporated board temperature ( c) 0 20 40 60 80 100 120 140 0 5 10 15 20 25 g028 v = 5v gs v = 12v v = 1.3v f = 500khz l = 1 h in out sw out m output current (a) 1 2 3
CSD87330Q3D www.ti.com slps284b C august 2011 C revised september 2011 recommended pcb design overview there are two key system-level parameters that can be addressed with a proper pcb design: electrical and thermal performance. properly optimizing the pcb layout will yield maximum performance in both areas. a brief description on how to address each parameter is provided. electrical performance the power block has the ability to switch voltages at rates greater than 10kv/ s. special care must be then taken with the pcb layout design and placement of the input capacitors, driver ic, and output inductor. ? the placement of the input capacitors relative to the power block s vin and pgnd pins should have the highest priority during the component placement routine. it is critical to minimize these node lengths. as such, ceramic input capacitors need to be placed as close as possible to the vin and pgnd pins (see figure 34 ). the example in figure 34 uses 6 10- f ceramic capacitors (tdk part # c3216x5r1c106kt or equivalent). notice there are ceramic capacitors on both sides of the board with an appropriate amount of vias interconnecting both layers. in terms of priority of placement next to the power block, c5, c7, c19, and c8 should follow in order. ? the driver ic should be placed relatively close to the power block gate pins. t g and b g should connect to the outputs of the driver ic. the t gr pin serves as the return path of the high-side gate drive circuitry and should be connected to the phase pin of the ic (sometimes called lx, ll, sw, ph, etc.). the bootstrap capacitor for the driver ic will also connect to this pin. ? the switching node of the output inductor should be placed relatively close to the power block vsw pins. minimizing the node length between these two components will reduce the pcb conduction losses and actually reduce the switching noise level. in the event the switch node waveform exhibits ringing that reaches undesirable levels, the use of a boost resistor or rc snubber can be an effective way to easily reduce the peak ring level. the recommended boost resistor value will range between 1.0 ohms to 4.7 ohms depending on the output characteristics of driver ic used in conjunction with the power block. the rc snubber values can range from 0.5 ohms to 2.2 ohms for the r and 330pf to 2200pf for the c. please refer to ti app note slup100 for more details on how to properly tune the rc snubber values. the rc snubber should be placed as close as possible to the vsw node and pgnd see figure 34 (1) (1) keong w. kam, david pommerenke, emi analysis methods for synchronous buck converter emi root cause analysis , university of missouri C rolla copyright ? 2011, texas instruments incorporated submit documentation feedback 13
CSD87330Q3D slps284b C august 2011 C revised september 2011 www.ti.com thermal performance the power block has the ability to utilize the gnd planes as the primary thermal path. as such, the use of thermal vias is an effective way to pull away heat from the device and into the system board. concerns of solder voids and manufacturability problems can be addressed by the use of three basic tactics to minimize the amount of solder attach that will wick down the via barrel: ? intentionally space out the vias from each other to avoid a cluster of holes in a given area. ? use the smallest drill size allowed in your design. the example in figure 34 uses vias with a 10 mil drill hole and a 16 mil capture pad. ? tent the opposite side of the via with solder-mask. in the end, the number and drill size of the thermal vias should align with the end user s pcb design rules and manufacturing capabilities. figure 34. recommended pcb layout (top down) 14 submit documentation feedback copyright ? 2011, texas instruments incorporated
CSD87330Q3D www.ti.com slps284b C august 2011 C revised september 2011 mechanical data q3d package dimensions millimeters inches dim min max min max a 1.40 1.5 0.055 0.059 b 0.280 0.400 0.011 0.016 c 0.150 0.250 0.006 0.010 c1 0.150 0.250 0.006 0.010 d 0.940 1.040 0.037 0.041 d1 0.160 0.260 0.006 0.010 d2 0.150 0.250 0.006 0.010 d3 0.250 0.350 0.010 0.014 d1 3.200 3.400 0.126 0.134 d2 2.650 2.750 0.104 0.108 e 3.200 3.400 0.126 0.134 e1 3.200 3.400 0.126 0.134 e2 1.750 1.850 0.069 0.073 e 0.650 typ 0.026 typ l 0.400 0.500 0.016 0.020 0.00 C C C k 0.300 typ 0.012 typ copyright ? 2011, texas instruments incorporated submit documentation feedback 15 m0192-01 e1 e q 5 6 7 8 1 2 3 4 l d1 d2 k b d3 l e a e2 d2 top view bottom view side view 5 9 6 7 8 1 2 3 4 q c1 d1 d c exposed tie clips may vary pinout position designation pin 1 v in pin 2 v in pin 3 t g pin 4 t gr pin 5 b g pin 6 v sw pin 7 v sw pin 8 v sw pin 9 p gnd
CSD87330Q3D slps284b C august 2011 C revised september 2011 www.ti.com land pattern recommendation note: dimensions are in mm (inches). stencil recommendation note: dimensions are in mm (inches). for recommended circuit layout for pcb designs, see application note slpa005 C reducing ringing through pcb layout techniques . 16 submit documentation feedback copyright ? 2011, texas instruments incorporated 0.200 (0.008) 0.350 (0.014) 0.210(0.008) 1 4 5 8 m0193-01 0.440 (0.017) 0.210 (0.008) 1.900 (0.075) 0.300 (0.012) 0.650 (0.026) 0.650 (0.026) 3.600 (0.142) 2.800 (0.110) 0.650(0.026) 1.090 (0.043) 2.390 (0.094) 0.300 (0.012) 0.300 (0.012) 0.300(0.012) 1 4 5 8 m0207-01 0.340 (0.013) 0.333(0.013) 0.100(0.004) 3.500 (0.138) 0.160 (0.005) 0.200 (0.008) 0.550 (0.022) 2.290 (0.090) 0.350 (0.014) 0.850 (0.033) 0.990 (0.039)
CSD87330Q3D www.ti.com slps284b C august 2011 C revised september 2011 q3d tape and reel information notes: 1. 10-sprocket hole-pitch cumulative tolerance 0.2 2. camber not to exceed 1mm in 100mm, noncumulative over 250mm 3. material: black static-dissipative polystyrene 4. all dimensions are in mm, unless otherwise specified. 5. thickness: 0.30 0.05mm 6. msl1 260 c (ir and convection) pbf reflow compatible spacer revision history changes from original (august 2011) to revision a page ? remove z ds(on) max values .................................................................................................................................................. 3 ? remove z ds(on) max values ................................................................................................................................................ 10 ? add electrical performance bullet ....................................................................................................................................... 13 ? changed dim a max dimensions ....................................................................................................................................... 15 changes from revision a (september 2011) to revision b page ? change sync fet uis to 157 mj ........................................................................................................................................ 2 ? change control fet rg typ/max to 1.5/3 ........................................................................................................................... 3 ? change hs r ds(on) typ/max to 9.4/11.3 ............................................................................................................................. 10 ? change ls r ds(on) typ/max to 4.7/5.7 ................................................................................................................................ 10 copyright ? 2011, texas instruments incorporated submit documentation feedback 17 4.00 0.10 (see note 1) 2.00 0.05 3.60 3.60 1.30 1.75 0.10 m0144-01 8.00 0.10 12.00 +0.30 C0.10 5.50 0.05 ? 1.50 +0.10 C0.00
package option addendum www.ti.com 5-nov-2011 addendum-page 1 packaging information orderable device status (1) package type package drawing pins package qty eco plan (2) lead/ ball finish msl peak temp (3) samples (requires login) CSD87330Q3D active son dqz 8 2500 pb-free (rohs exempt) cu sn level-1-260c-unlim (1) the marketing status values are defined as follows: active: product device recommended for new designs. lifebuy: ti has announced that the device will be discontinued, and a lifetime-buy period is in effect. nrnd: not recommended for new designs. device is in production to support existing customers, but ti does not recommend using this part in a new design. preview: device has been announced but is not in production. samples may or may not be available. obsolete: ti has discontinued the production of the device. (2) eco plan - the planned eco-friendly classification: pb-free (rohs), pb-free (rohs exempt), or green (rohs & no sb/br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. tbd: the pb-free/green conversion plan has not been defined. pb-free (rohs): ti's terms "lead-free" or "pb-free" mean semiconductor products that are compatible with the current rohs requirements for all 6 substances, including the requirement that lead not exceed 0.1% by weight in homogeneous materials. where designed to be soldered at high temperatures, ti pb-free products are suitable for use in specified lead-free processes. pb-free (rohs exempt): this component has a rohs exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. the component is otherwise considered pb-free (rohs compatible) as defined above. green (rohs & no sb/br): ti defines "green" to mean pb-free (rohs compatible), and free of bromine (br) and antimony (sb) based flame retardants (br or sb do not exceed 0.1% by weight in homogeneous material) (3) msl, peak temp. -- the moisture sensitivity level rating according to the jedec industry standard classifications, and peak solder temperature. important information and disclaimer: the information provided on this page represents ti's knowledge and belief as of the date that it is provided. ti bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. efforts are underway to better integrate information from third parties. ti has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. ti and ti suppliers consider certain information to be proprietary, and thus cas numbers and other limited information may not be available for release. in no event shall ti's liability arising out of such information exceed the total purchase price of the ti part(s) at issue in this document sold by ti to customer on an annual basis.
tape and reel information *all dimensions are nominal device package type package drawing pins spq reel diameter (mm) reel width w1 (mm) a0 (mm) b0 (mm) k0 (mm) p1 (mm) w (mm) pin1 quadrant CSD87330Q3D son dqz 8 2500 330.0 12.8 3.6 3.6 1.75 8.0 12.0 q1 package materials information www.ti.com 1-oct-2011 pack materials-page 1
*all dimensions are nominal device package type package drawing pins spq length (mm) width (mm) height (mm) CSD87330Q3D son dqz 8 2500 335.0 335.0 32.0 package materials information www.ti.com 1-oct-2011 pack materials-page 2
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